The present invention relates to circuits for synchronizing data transfer between clock domains of the same frequency but different phase, in particular for synchronous memory systems.
Mesochronous systems consist of two or more different clocks running at the same frequency with an arbitrary phase relationship. In such systems synchronization failures-can occur when passing data from one clock domain into another. While this problem is similar to that of asynchronous systems, it is easier to solve in that both clocks are running at the same frequency. It is possible to achieve reliable lower latency data transfer than is possible in asynchronous systems because of this constraint.
Computer systems typically use a bus to transmit data between separate components. In order to transmit data at the highest rates with the lowest latency, synchronous transmission is frequently used. In one embodiment (see FIG. 1), a transmit clock is sent along with the data signal down a bus until it reaches the receiving device where it can be used to clock the data. This is done so that the delay the signal sees when traveling down the bus wire is matched by the delay of the clock traveling down a matched bus wire. If the same technique is used to send clock and data in both directions, then the transmit and receive data (and clocks) can have phase relationships that depend on the position of the device along the bus. When crossing from the receive clock domain to the transmit clock domain inside the part, it becomes necessary to re-time the data, or at least to re-time a control pulse to the transmit clock domain. Prior art implementations placed restrictions on the length of such buses. In bussed systems such as FIG. 1, the length of a bus determines the phase relationship between receive and transmit clocks.
It is convenient to view any phase difference between two mesochronous clocks as a fraction of the clock cycle time. With two clocks of cycle-time TCYCLE and with phase relative to the source defined as tTxClk for the transmit clock and tRClk for the receive clock (see FIG. 5) then tTR is the relative phase between the falling edges of the clocks as a fraction of the clock cycle time and can be represented as:       t    TR    =                    t        RClk            -              t        TxClk                    t      CYCLE      
With this definition, the phase position of two clocks with exactly the same relationship would be tTR=0, and two clocks who are inverted from each other would be tTR=0.5, etc. U.S. Pat. No. 5,432,823 to Gasbarro uses a fixed latency protocol to provide output data at a consistent latency despite clock skews. Because of limitations in circuit performance, the maximum skew, and thus bus length in one embodiment of Gasbarro (see FIG. 2) has a tTR limit. If a device was placed beyond this limit, its output data latency could be uncertain, as the internal synchronization circuits would be near their failure point. Prior art, using a fixed-latency protocol does not provide control for the transition from one latency to another. To eliminate this occurrence, limitations are sometimes placed on the tTR range of operation, and thus potentially on the maximum bus length and device count.
Another system is described in copending application Ser. No. 08/897,658 of Portmann et. al., filed Jul. 21, 1997 now U.S. Pat. No. 6,205,191, and commonly assigned with this application (see FIG. 3). Portmann describes chains of flip-flops which can gradually be used to re-time data from one domain to another. Such re-timing systems are actually a subset of the arbitrary-phase problem; the skew between clocks in Portmann can be easily recreated by adding a matching delay chain on-chip. Such systems also suffer from large latency from input to output data, as each flip-flop in the chain can add another cycle of output latency. They also suffer from the same uncertainty at the latency domain switching-point as Gasbarro, and so are unsuitable for use in systems with arbitrary phase-relationships between clocks, such as would be encountered in long-buses.
The present invention allows for unlimited tTR. By supporting a mixed-latency protocol it allows for tTR greater than 1.0 without uncertainty concerns by creating firm latency domains. Unlike prior art, it maintains the output latency chosen during initialization despite any Vdd or temperature variations that may later occur. In addition, this invention includes circuits that allow operation at higher frequencies than prior art.
The present invention provides a synchronization circuit having two latching circuits which latch data from a receive clock domain on both the rising and falling edges of a transmit clock. The selection of which latch data to use is based on a phase measurement of the phase difference between the receive and transmit clocks, which provides a select signal to a multiplexer connected to the two latching circuits. The phase difference is chosen to provide data which is as close as possible to the middle of an overlap region of valid data for the two latches. Once this value has been chosen, it is frozen in a latch after initialization. Since the data could have one, two or more clock cycle latencies from its origin, freezing the clock selection also freezes the latency period for operation of the circuit. Thus, although the synchronization circuit only knows the relative phase difference, not the latency, it can establish a stable operating configuration.
The terms xe2x80x9creceivexe2x80x9d and xe2x80x9ctransmitxe2x80x9d clock domains refer to reception and transmission by the synchronization circuit, and does not necessarily correspond to received and transmitted data by a device, such as a memory device. The invention is particularly useful in a synchronous memory system in which multiple DRAM are placed along a synchronous bus, at varying latencies from a clock origination point. The re-clocked data at each individual DRAM could be in a first latency period or a second latency period. The overall system may be equalized by adding latency to devices having less of a latency period to thus provide that all the data will be placed on the bus at the same time.
In a preferred embodiment, the receive clock domain data is provided through a flip-flop clocked by a receive clock. The two latching circuits are preferably flip-flops utilizing a precharged sense amp in order to minimize shifting of the clock due to set-up, hold and clock-to-data-out variations.
Preferably, the phase measurement circuit has a phase comparator coupled to receive the receive clock and also a clock which is in quadrature with the transmit clock, rather than the transmit clock itself, in order to place the ultimate skip signal at the point of maximum overlap of valid data. The output of the phase comparator is provided to an integrator in order to remove any jitter and narrow any uncertainty in the decision point. Preferably, an external transmit clock is used, rather than one that has been synchronized using a DLL or PLL, in order to eliminate another possible source of jitter. For a further understanding of the nature and advantages of the invention, reference should be made to the following description taken in conjunction with the accompanying drawings.